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IN74LV14
HEX SCHMITT-TRIGGER INVERTER
The 74LV14 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT14. The 74LV14 provides six inverting buffers with Schmitttrigger action. * * * * Wide Operating Voltage: 1.0 to 5.5 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low input current ORDERING INFORMATION IN74LV14N Plastic IN74LV14D SOIC IZ74LV14 Chip TA = -40 / 125 C for all packages
LOGIC DIAGRAM PIN ASSIGNMENT
PIN PIN 7 = GND
14
=VCC
FUNCTION TABLE Input Output A Y= A L H H L
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IN74LV14
MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC supply voltage (Referenced to GND) V -0.5 / +7.0 1 IIK* DC input diode current mA 20 IOK*2 DC output diode current mA 50 3 Io* DC output source or sink current mA 25 -bus driver outputs IGND DC GND current for types with mA 50 - bus driver outputs ICC DC VCC current for types with mA 50 - bus driver outputs 750 mW PD Power dissipation per paskade, plastic DIP+ 500 SOIC package+ Tstg Storage temperature -65 / +150 C 260 TL Lead temperature, 1.5 mm from Case for 10 C seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C 1 * : VI < -0.5V or VI > VCC+0.5V *2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 1.0 5.5 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to 0 VCC V GND) TA Operating Temperature, All Package Types -40 +125 C ns 500 t r, tf Input Rise and Fall Time 0 1.0 VVCC <2.0 V 200 0 2.0 VVCC <2.7 V 100 0 2.7 VVCC <3.6 V 50 0 3.6 VVCC 5.5 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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IN74LV14
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Test VCC 25C -40C / -40C / Symbol Parameter Conditio V 85C 125C ns min max min max min max 1.0 0.4 1.0 0.4 VIT+ Positive-Going VO VOH 1.2 0.45 0.95 1.4 0.8 1.4 0.8 Input 2.0 0.85 1.35 2.0 1.0 2.0 1.0 Threshold 2.7 1.05 1.95 2.2 1.2 2.2 1.2 Voltage 3.0 1.25 2.15 2.4 1.5 2.4 1.5 3.6 1.55 2.35 3.15 1.7 3.15 1.7 4.5 1.75 3.10 3.85 2.1 3.85 2.1 5.5 2.15 3.80 0.7 0.15 0.7 0.65 0.15 0.2 VITNegative1.2 VO VOL 0.9 0.3 0.9 0.3 Going Input 2.0 0.35 0.85 1.4 0.4 1.4 0.4 Threshold 2.7 0.45 1.35 1.5 0.6 1.5 0.6 Voltage 3.0 0.65 1.45 1.8 0.8 1.8 0.8 3.6 0.85 1.75 2.0 0.9 2.0 0.9 4.5 0.95 1.95 2.26 1.1 2.26 1.1 5.5 1.15 1.15 0.7 0.15 0.7 0.65 0.15 0.2 VH Hysteresis VO VOH 1.2 0.9 0.3 0.9 0.3 Voltage 2.0 0.25 0.75 VO VOL 1.4 0.4 1.4 0.4 2.7 0.35 1.05 1.5 0.6 1.5 0.6 3.0 0.45 1.15 1.8 0.8 1.8 0.8 3.6 0.45 1.15 2.0 0.9 2.0 0.9 4.5 0.45 1.35 2.6 1.1 2.6 1.1 5.5 0.65 1.45 1.0 1.0 VOH High-Level VI = VIH - 1.2 1.05 1.8 1.8 2.0 1.85 Output Voltage or VIL 2.5 2.5 IO = -100 2.7 2.55 2.8 2.8 3.0 2.85 A 3.4 3.4 3.6 3.45 4.3 4.3 4.5 4.35 5.3 5.3 5.5 5.35 2.40 2.20 VOH High-Level VI = VIH - 3.0 2.48 Output Voltage or VIL IO = -6.0 mA VI = VIH - 4.5 3.70 3.60 3.50 or VIL IO = -12.0 mA 0.2 0.2 0.15 VOL Low-Level VI = VIH - 1.2 0.2 0.2 0.15 2.0 Output Voltage or VIL 0.2 0.2 0.15 IO = 100 2.7 0.2 0.2 0.15 3.0 A 0.2 0.2 0.15 3.6 0.2 0.2 0.15 4.5 0.2 0.2 0.15 5.5
Unit V
V
V
V
V
V
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IN74LV14
DC ELECTRICAL CHARACTERISTICS (continuation) Symbol VOL Parameter Low-Level Output Voltage Test Conditio ns VCC V 25C Guaranteed Limit -40C / -40C / 85C 125C max min max min max 0.33 0.40 0.50 Unit
min VI = VIH - 3.0 V or IO = 6.0 mA VI = VIH - 4.5 0.40 0.55 0.65 or VIL IO = 12.0 mA IIL Low-Level Input VI=0 V 5.5 -0.1 -1.0 -1.0 A Leakage Current IIH High-Level Input VI= V 5.5 0.1 1.0 1.0 Leakage Current VI=0 or 5.5 4.0 20 40 ICC Quiescent A Supply Current V (per Package) IO = 0 A VI = V - 2.7 0.2 0.5 0.85 mA ICC1 Additional 3.6 Quiescent 0.6V Supply Current IO = 0 A on input .AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH =tHL = 2.5 ns, RL=1 k) Guaranteed Limit Test VCC 25C -40C / -40C / Unit Symbol Parameter Conditio V 85C 125C ns min max min max min max ns 200 170 150 VI=0 V or 1.2 tPLH, tPHL Propagation 48 37 28 2.0 Delay, Input V1 35 28 22 A to Output Y tLH = tHL 2.7 28 22 17 (Figure 1 ) =2.5 ns 3.0 23 18 14 L = 50 4.5 pF RL = 1 k CI Input 5.5 7.0 7.0 7.0 pF Capacitance CPD VI=0 V or 5.5 30 30 30 pF V
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IN74LV14
tHL
0.9 VX 0.1 0.9 VX 0.1
tLH V1 GND
Input
tPHL
tPLH
VOH Output Y
VY VY
VOL
VX=0.5 VCC Figure 1. Switching Waveforms
VCC
VI PULSE GENERATOR DEVICE UNDER TEST
VO
Termination resistance RT - should be equal to ZOUT of pulse generators
CL RL
RT
Figure 2. Test Circuit
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IN74LV14
CHIP PAD DIAGRAM IZ74LV14
1.33 0.03
13
12
11
10
09
1.42 0.03
14
08 07
01 02 03 04 05 06
Chip marking IN74LV14 (x=0.130; y=0.130)
Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol A1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 VCC X 0.130 0.130 0.381 0.616 0.881 1.116 1.115 1.115 1.115 0.804 0.569 0.378 0.143 0.130 Y 0.463 0.230 0.126 0.126 0.126 0.126 0.631 0.846 1.181 1.194 1.194 1.194 1.194 0.813
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